Biography

Dr. Geoff Knagge received the B. Comp. Sci degree (2001) and B.E. (Hons I) in Computer Engineering (2002) from the University of Newcastle, Australia. He was also awarded his PhD by the University of Newcastle in 2007, and also received the Faculty award for Research Higher Degree Excellence for his thesis work. He is currently working with their Signal Processing and Microelectronics Group. His general research areas include digital processor and low power VLSI design, with emphasis on applications relating to baseband processing for digital wireless communications technologies. He is an author on 2 journal articles, 8 published conference papers, 1 US patent, and an additional pending patent.

Projects

My PhD thesis covered topics in the following general areas:

• Digital VLSI implementations and low power techniques
• Practical algorithms for digital communications and improving feasibility VLSI implementation
• Near optimal algorithms for combinatorial optimisation in VLSI, with application to multiuser detection and MIMO.

Specifically, the major component involved developing a VLSI solution for higher order detection problems, using an optimised low-computation "spherical" based search. As a proof of concept, an ASIC design for an 8x8 MIMO detector was created, synthesised, and routed, although the device has not yet been fabricated.

This involved research into a number of subcomponents, including

• Power efficient multiplier circuits
• QR decomposition and preprocessing for the sphere search in VLSI
• High speed sorting techniqures in VLSI

My current work is with the Model-Predictive Control project, and extending this postgraduate work, that dealt with combinatorial optimisation in VLSI. Part of this has involved the development of

• The c4HDL project, to allow easy bit accurate modelling of hardware performance, using C++
• The c4Hardware project, which uses c4HDL to provide bit accurate or limited precision estimation of algorithm performance.